Booster power generating circuit

ABSTRACT

A booster power generating circuit according to the present invention comprises first to fourth booster circuits for supplying first to fourth booster potentials to first to fourth nodes in response to first to fourth pulse signals, a first precharge circuit for precharging the first node when controlled by the fourth booster potential from the fourth node, a second precharge circuit for precharging the third node when controlled by the second booster potential from the second node and a first output circuit for outputting the first booster potential of the first node to an output node, whereby a given booster potential can be output since there is no voltage drop of the boosted potential of the second and fourth nodes, there is obtained high potential between the first and third precharge circuits and the precharging speed of the first and third node is not slowed.

TECHNICAL FIELD

The present invention relates to a booster power generating circuit of asemiconductor, particularly to a booster power generating circuit forgenerating a given booster potential.

BACKGROUND OF THE INVENTION

A known booster power generating circuit is exemplified in FIG. 2. Acircuit arrangement of this booster power generating circuit will bedescribed with reference to FIG. 2.

The booster power generating circuit comprises a signal generatingcircuit 1 for generating complementary first and second pulse signals S1and S2 and a charge pump circuit 10 for transferring a given boosterpotential to the load from an output node N3 in response to the firstand second pulse signals S1 and S2.

The charge pump circuit 10 comprises first and second inverters 11-1 and11-2, first and second capacitors 12-1 and 12-2, first to fourthN-channel MOSFETs (hereinafter referred to as NMOS) 13-1, 13-2, 13-3 and13-4 and first and second P-channel MOSFETs (hereinafter referred toPMOS) 14-1 and 14-2.

The first and second inverters 11-1 and 11-2 drive respectively thefirst and second pulse signals S1 and S2 which are output from thesignal generating circuit 1, thereby outputting third and fourth pulsesignals S3 and S4. The first capacitor 12-1 is connected to the outputside of the first inverter 11-1 for boosting the potential of first nodeN1 in response to the third pulse signal S3. The second capacitor 12-2is connected to the output side of the second inverter 11-2 for boostingthe potential of second node N2 in response to the fourth pulse signalS4. The first node N1 is connected to each source of the first andsecond NMOSs 13-1 and 13-2 which precharge the first node N1 and alsoconnected to the drain of the first PMOS 14-1 which transfers thepotential of the first node N1 to the output node N3. The first NMOS13-1 is connected to a power potential Vcc at its drain and alsoconnected to the second node N2 at its gate. The second NMOS 13-2 isconnected to the power potential Vcc at its drain and gate. The secondnode N2 is connected to each source of the third and fourth NMOSs 13-3and 13-4 which precharge the second node N2 and also connected to thedrain of the second PMOS 14-2 for transferring the potential of thesecond node N2 to the output node N3. The third NMOS 13-3 is connectedto the power potential Vcc at its drain and also connected to the firstnode N1 at its gate. The fourth NMOS 13-4 is connected to the powerpotential Vcc at its drain and gate.

The charge pump circuit 10 is set under the following circuit condition.

Supposing a threshold potential of each of the first to fourth NMOSs13-1 to 13-4 are represented as vtn and a threshold potential of each ofthe first and second PMOSs 14-1 and 14-2 are represented as vtp.Potential φp of the load, to be connected to the output node N3,depending on charge consumption I is represented as φp=2Vcc-vtp in caseof I=0 while it is represented as φp=2Vcc-vtp-α in case of I=0.Supposing that capacitance of each of the first and second capacitors12-1 and 12-2 is represented as Cp, parasitic capacitance of each of thefirst and second nodes N1 and N2 is represented as Cs, potential changeof each of the third and fourth pulse signals S3 and S4 is representedas δV and potential change of each of the first and second nodes N1 andN2 is represented as δN, the following equation is established. ##EQU1##where, Cp>>Cs and δN=δV

SUMMARY OF THE INVENTION

A booster power generating circuit according to a first aspect of theinvention comprises first to fourth booster circuits for supplying firstto fourth booster potentials to first to fourth nodes in response tofirst to fourth pulse signals, a first precharge circuit for prechargingthe first node upon reception of the fourth booster potential from thefourth node, a second precharge circuit for precharging the third nodeupon reception of the second booster potential from the second node anda first output circuit for outputting the first booster potential of thefirst node to an output node.

A booster power generating circuit according to a second aspect of theinvention comprises a first booster circuit provided with a firstcapacitor having first capacitance for supplying a first boosterpotential to a first node in response to a first pulse signal, a secondbooster circuit provided with a capacitor having second capacitancewhich is smaller than the first capacitance for supplying a secondbooster potential to a second node in response to a second pulse signal,a third booster circuit provided with a third capacitor having thirdcapacitance for supplying a third booster potential to a third node inresponse to a third pulse signal, and a fourth booster circuit providedwith a fourth capacitor having fourth capacitance which is smaller thanthe third capacitance for supplying a fourth booster potential to afourth node in response to a fourth pulse signal.

A booster power generating circuit according to a third aspect of theinvention comprises a first switching circuit for outputting a firstbooster potential of a first node to an output node upon reception of afifth booster potential from a fifth node and a second switching circuitfor outputting a second booster potential of a second node to the outputnode upon reception of a sixth booster potential from a sixth node.

A booster power generating circuit according to a fourth aspect of theinvention comprises a first precharge circuit for precharging a firstnode upon reception of a fourth booster potential from a fourth node, asecond precharge circuit for precharging a third node upon reception ofa second booster potential from a second node, a first output circuitfor outputting second and fourth booster potentials of second and fourthnodes and a second output circuit for outputting first and third boosterpotentials of first and third nodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a booster power generating circuitaccording to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a conventional booster power generatingcircuit;

FIG. 3 is a circuit diagram of a signal generating circuit in thebooster power generating circuit in FIG. 1;

FIG. 4 is a timing chart explaining the operation of the booster powergenerating circuit in FIG. 1;

FIG. 5 is a circuit diagram of a booster power generating circuitaccording to a second embodiment of the invention;

FIG. 6 is a timing chart explaining the operation of the booster powergenerating circuit in FIG. 5;

FIG. 7 is a circuit diagram of a booster power generating circuitaccording to a third embodiment of one invention; and

FIG. 8 is a timing chart explaining the operation of the booster powergenerating circuit in FIG. 7.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a circuit diagram of a booster power generating circuitaccording to a first embodiment of the present invention. Thearrangement of the booster power generating circuit of the firstembodiment will be described with reference to FIGS. 1, 3 and 4.

The booster power generating circuit comprises a signal generatingcircuit 100 for outputting complementary first and second pulse signalsS11 and S12 and a charge pump circuit 200 for generating a given boosterpotential in response to the first and second pulse signals S11 and S12and outputting the thus generated booster potential to the loadconnected to an output node NO.

The charge pump circuit 200 comprises first, second, third and fourthbooster circuits 210, 220, 230, and 240 for boosting potentials offirst, second, third and fourth nodes N11, N12, N13 and N14 in responseto the first and second pulse signals S11 and S12, first, second, thirdand fourth precharge circuits 310, 320, 330 and 340 for precharging thefirst, second, third and fourth nodes N11, N12, N13 and N14 and firstand second output circuits 410 and 420 for outputting the boostedpotentials of the first and third nodes N11 and N13 to the output nodeNO.

The first booster circuit 210 has an inverter 211 for driving the firstpulse signal S11 output from the signal generating circuit 100 tothereby output a third pulse signal S13. An output side of the inverter211 is connected to the first node N11 by way of a first capacitor 212which boosts the potential of the first node N11 in response to thethird pulse signal S13.

The second booster circuit 220 has an inverter 221 for driving the firstpulse signal S11 in the same manner as the first booster circuit 210 foroutputting a fourth pulse signal S14. An output side of the inverter 221is connected to the second node N12 by way of a second capacitor 222which boosts the potential of the second node N12 in response to thefourth pulse signal S14.

The third booster circuit 230 has an inverter 231 for driving the secondpulse signal S12 to thereby output a fifth pulse signal S15. An outputside of the inverter 231 is connected to a third node N13 by way of athird capacitor 232 which boosts the potential of the third node N13 inresponse to the fifth pulse signal S15.

The fourth booster circuit 240 has an inverter 241 for driving thesecond pulse signal S12 in the same manner as the third booster circuit230 for outputting a sixth pulse signal S16. An output side of theinverter 241 is connected to the fourth node N14 in response to thesixth pulse signal S16.

The first precharge circuits 310 comprises an NMOS 311 gate of which iscontrolled by the potential of the fourth node N14. The NMOS 311 isconnected to the first node N11 at its source and also connected to apower potential Vcc at its drain.

The second precharge circuit 320 comprises an NMOS 321 for prechargingthe second node N12 and an NMOS 322 gate of which is controlled by thefourth node N14. Sources of each of the NMOSs 321 and 322 arerespectively connected to the second node N12 and the gate and drain ofthe NMOS 321 are connected to the power potential Vcc while the drain ofthe NMOS 322 is connected to the power potential Vcc.

The third precharge circuits 330 comprises an NMOS 331 gate of which iscontrolled by the potential of the fourth node N12. The NMOS 331 isconnected to the third node N13 at its source and also connected to apower potential Vcc at its drain.

The fourth precharge circuit 340 comprises an NMOS 341 for prechargingthe fourth node N14 and an NMOS 342 gate of which is controlled by thesecond node N12. Sources of each of the NMOSs 341 and 342 arerespectively connected to the fourth node N14 and the NMOS 341 isconnected to the power potential Vcc at its gate and drain while theNMOS 342 is connected to the power potential Vcc at its drain.

The first output circuit 410 comprises a PMOS 411 for outputting theboosted potential of the first node N11 to the output node NO. The PMOS411 is connected to the output node NO at its source and gate and alsoconnected to the first node N11 at its drain.

The second circuit 420 comprises a PMOS 421 for outputting the boostedpotential of the third node N13 to the output node NO in the same manneras the first output circuit 410. The PMOS 421 is connected to the outputnode NO at its source and gate and also connected to the third node N13at its drain.

FIG. 3 is a circuit diagram of a signal generating circuit in thebooster power generating circuit in FIG. 1.

The signal generating circuit comprises a ring oscillator 110 and aflip-flop circuit (hereinafter referred to as FF) 120 connected to theoutput side of the ring oscillator 110 for outputting the first andsecond pulse signals S11 and S12.

The ring oscillator 110 comprises a plurality of odd numbers ofinverters 111 to 115 which are connected to one another in a ring-likearrangement wherein the inverter 115 is connected at is input and outputsides to the FF 120. The FF 120 comprises two 2-input NAND gates 121 and122 which are connected to each other in a cross-linking manner. Oneinput side of the NAND gate 121 is connected to the output side of theinverter 115 of the ting oscillator 110 while the other input sidethereof is connected to the output side of the NAND gate 122. One inputside of the NAND gate 122 is connected to the output side of theinverter 114 of the ring oscillator 110 while the other input sidethereof is connected to the output side of the NAND gate 121.

Complementary signals are output from the ring oscillator 110 of thesignal generating circuit 100 when the signal generating circuit 100oscillates. The FF 120 is set or reset in response to the signals issuedby the ring oscillator 110 to thereby output the complementary first andsecond pulse signals S11 and S12 in a given timing.

FIG. 4 is a timing chart explaining the operation of the booster powergenerating circuit in FIG. 1.

Supposing that each threshold potential of the NMOSs 311, 321, 322, 331,341 and 342 is vtn and each threshold potential of the PMOSs 411 and 421is vtp.

At time t1, the pulse signals S11, S15 and S16 are in the powerpotential Vcc and the pulse signals S12, S13 and S14 are in the groundpotential Vss while the nodes N11 and N12 are in the power potentialVcc, the node N13 is in the potential expressed by φp+vtp, the node N14is in the doubled power potential Vcc, i.e., 2Vcc and the node NO is inthe output potential φp.

At time t2, if the second pulse signal S12 is changed from the groundpotential Vss to the power potential Vcc, the pulse signals S15 and S16which are driven by the inverters 231 and 241 are changed from the powerpotential Vcc to the ground potential Vss. The potential of the node N13is changed to the potential expressed by φp+vtp-Vcc by the thirdcapacitor 232 when the latter receives the pulse signal S15. Thepotential of the node N14 is changed to the power potential Vcc by thecapacitor 242 when the latter receives the pulse signal S16. At thistime, when the potential of the node N13 becomes less than the potentialexpressed by Vcc-vtn, the NMOS 331 is turned on so that the potential ofthe node N13 is charged until it reaches the potential expressed byVcc-vtn.

At time t3, if the first pulse signal S11 is changed from the powerpotential Vcc to the ground potential Vss, the third and fourth pulsesignals S13 and S14 which are driven by the inverters 211 and 221 arechanged from the ground potential Vss to the power potential Vcc. Thepotential of the node N11 is boosted to the potential of 2Vcc by thecapacitor 212 when the latter receives the third pulse signal S13 whilethe potential of the node N12 is boosted to the potential of 2Vcc by thecapacitor 222 when latter receives the fourth pulse signal S14. At thistime, when the potential of the node N12 exceeds the potential expressedby Vcc+vtn, the NMOSs 311 and 342 are turned on so that the potentialsof the nodes N13 and N14 are charged until it reaches the powerpotential Vcc. When the potential of the node N11 exceeds the potentialexpressed by φp+vtp, the PMOS 411 is turned on so that the output nodeNO is charged until it reaches the output potential φp owing to theaccumulated charge of the node N11. At the same time, the node N11 emitsthe charge and its potential is changed to the potential expressed byφp+vtp. At this time, the node N12 does not use its accumulated chargefor charging the output node NO and hence its potential is kept to be2Vcc. Accordingly, there are obtained the potential difference exceedingthe power potential Vcc between gates and sources of the NMOSs 331 and342 so that the potentials of the nodes N13 and N14 are charged quicklyuntil they reach the power potential Vcc.

Furthermore, it is possible to lessen the capacitance of the capacitor222 without depending on the charge consumption of the output node NOsince the accumulated charge of the node N12 is not used for chargingthe output node NO. Still furthermore, the inverter 221 for driving thepulse signal S14 which is input to the capacitor 222 is separated fromthe inverter 211 for driving the pulse signal S13 which is input to thecapacitor 212. Accordingly, the potential change of the fourth pulsesignal S14 is not slowed by the capacitance of the first capacitor 212.The potential change of the fourth pulse signal S14 is not slowed by thecapacitance of the second capacitor 222 since the capacitance of thesecond capacitor 222 is small. Accordingly, the output potential φp isnot lowered.

After time t3, the same operations which are performed during times t1to t3 are repeated between the first and second pulse signals S11 andS12.

The first embodiment of the present invention has the following effects.

(a) The first and third nodes N11 and N13 for supplying the charge tothe output node NO are separated from the second and fourth nodes N12and N14 for controlling the NMOS 311 and 331 which precharge these firstand third nodes N11 and N13. Accordingly, there are obtained highpotential difference between the gate and source of the NMOS 311 and 321whereby the output potential φp of the output node NO can be preventedfrom being lowered.

(b) The first and third capacitors 212 and 232 for boosting thepotentials of the first and third nodes N11 and N13 and the second andfourth capacitors 222 and 242 for boosting the potentials of the secondand fourth nodes N12 and N14 are separated from one another and thefirst and fourth inverters 211, 221, 231 and 241 for driving the firstto fourth pulse signals S13, S14, S15 and S16 which are input to thefirst to fourth capacitors 212, 222, 232 and 242 are separated from oneanother. Accordingly, the potential charging of the nodes N12 and N14can be made quickly, and hence the charges accumulated in the first andthird capacitors 212 and 232 are not discharged to the power potentialVcc by way of the first and third NMOSs 311 and 331. Accordingly, theoutput potential φp of the output node NO can be prevented from beinglowered.

FIG. 5 is a circuit diagram of a booster power generating circuitaccording to a second embodiment of the invention. The arrangement ofthe booster power generating circuit of the second embodiment will bedescribed with reference to FIG. 5.

The booster power generating circuit comprises a signal generatingcircuit 100 arrangement of which is the same as that of the firstembodiment and a charge pump circuit 200A arrangement of which isdifferent from that of the first embodiment.

The charge pump circuit 200A comprises first, second, third and fourthbooster circuits 210A, 220A, 230A, and 240A, first, second, third andfourth precharge circuits 310, 320, 330 and 340, first and second outputcircuits 410 and 420 and an auxiliary power circuit 500.

The first and third booster circuits 210A and 230A comprises first andsecond 2-input NAND gates 213 and 233 which are selectively controlledby a first control signal S21 and first and third capacitors 212 and232. The first control signal S21 is changed between the power potentialVcc and the ground potential Vss in response to the charge consumptionof the load which is connected to, i.e. the output node NO. The NANDgate 213 is connected to the first pulse signal S11 at its one inputside and to the control signal S21 at its other input side and it isalso connected to the third node N13 by way of the third capacitor 232at its output side.

The auxiliary power circuit 500 comprises a third output circuit 510 foroutputting the boosted potential of the second node N12 to the fifthnode N15, a fourth output circuit 520 for outputting the boostedpotential of the fourth node N14 to the fifth node N15 and a switchingmeans 530 for outputting the boosted potential of the fifth node N15 tothe output node NO. The third output circuit 510 comprises a PMOS 511for outputting the boosted potential of the second node N12 to the fifthnode N15. The PMOS 511 is connected to the second node N12 at its drainand to the fifth node N15 at its source and gate. The fourth outputcircuit 520 comprises a PMOS 521 for outputting the boosted potential ofthe fourth node N14 to the fifth node N15 in the same manner as thethird output circuit 510. The PMOS 521 is connected to the fourth nodeN14 at its drain and to the output node NO at its source and gate.

The switching means 530 comprises a PMOS 531 which is subjected toon/off control by the second control signal S22 which is synchronouswith the first control signal S21. The second control signal S22 ischanged between the potential of the fifth node N15 and the groundpotential Vss in response to the charge consumption of the load. ThePMOS 531 is connected to the fifth node N15 at its source and to theoutput node NO at its drain and to the second control signal S22 at itsgate.

The operations of the booster power generating circuit will be describedrespectively (1) in case of large charge consumption of the load, and(2) in case of small charge consumption of the load.

Supposing that the threshold potential of the NMOS in FIG. 5 is vtn andthe threshold potential of the PMOS is vtp.

(1) In case of large charge consumption:

In a normal case where the charge consumption of the load connected tothe output node NO is large, the control signal S22 is in the potentialexpressed by 2Vcc-vtp, the control signal S21 is in the power potentialVcc and the fifth node is in the potential expressed by 2Vcc-vtp whilethe PMOS 531 is turned off and the first and third booster circuits 210Aand 230A are active. The operation of the booster power generatingcircuit in this state is the same as the first embodiment.

(2) In case of small charge consumption:

FIG. 6 is a timing chart explaining the operation of the booster powergenerating circuit in FIG. 5 at the standby state where the chargeconsumption of the load is small. The booster power generating circuitaccording to the second embodiment will be described with reference toFIG. 6.

At time t1, the pulse signals S11 and S16 are in the power potential Vccand the pulse signals S12 and S14 are in the ground potential Vss whilethe nodes N11, N12 and N13 are in the power potential Vcc, the node N14is in the potential expressed by φp+vtp, the node N15 and the outputnode NO are respectively in the output potential φp.

At the standby state, the control signals S21 and S22 are always in theground potential Vss. Accordingly, the PMOS 531 is turned on and theNAND gates 213 and 233 are inactive and the pulse signals S13 and S15are kept in the power potential Vcc.

At time t2, if the second pulse signal S12 is changed from the groundpotential Vss to the power potential Vcc, the sixth pulse signal S16which is driven by the inverters 241 is changed from the power potentialVcc to the ground potential Vss. The potential of the node N14 ischanged to the potential expressed by φp+vtp-Vcc by the capacitor 242when the latter receives the pulse signal S16. At this time, when thepotential of the node N14 becomes less than the potential expressed byVcc-vtn, the NMOSs 341 and 342 are turned on so that the potential ofthe fourth node N14 is charged until it reaches the potential expressedby Vcc-vtn.

At time t3, if the first pulse signal S11 is changed from the powerpotential Vcc to the ground potential Vss, the pulse signal S14 which isdriven by the inverter 221 is changed from the ground potential Vss tothe power potential Vcc. The potential of the node N12 is boosted to thepotential of 2Vcc by the capacitor 222 when the latter receives thefourth pulse signal S14. At this time, when the potential of the nodeN12 exceeds the potential expressed by Vcc+vtn, the NMOS 342 is turnedon so that the potential of the node N14 is charged until it reaches thepower potential Vcc. When the potential of the node N12 exceeds thepotential expressed by φp+vtp, the PMOS 511 is turned on so that thenodes N15 and N16 are charged until they reach the output potential φpowing to the accumulated charge of the node N12. At the same time, thenode N12 emits the charge and its potential is changed to the potentialexpressed by φp+vtp.

At this time, the potential of the node N12 decreases from the potentialof 2Vcc, the mutual conductance gm of the NMOS 342 is lowered. However,since the node N12 supplies the charge at the standby state alone, thelowering of the output potential φp owing to the charge consumption issmall and the capacitance of the capacitor 222 can be lessened comparedwith that of the capacitor 212, the node N12 can be charged quickly.Accordingly, the output potential φp is not lowered.

After time t3, the same operations which are performed during times t1to t3 are repeated between the first and second pulse signals S11 andS12.

The booster power generating circuit according to the second embodimentof the present invention has the same effects as the first embodimentand also has the effect that the current consumption can be reducedsince the boosted current is supplied from the capacitors 222 and 242having small capacitance while the second and third capacitors 212 and232 having large capacitance are stopped at the standby state.

The present invention is not limited to the first and second embodimentsas set forth above but can be modified as follows.

(1) The NMOS and the PMOS of the charge pump circuits 200 and 200A maycomprise other transistors and the polarity of the power supply can bechanged.

(2) The width of the pulse signal may be varied by increasing ordecreasing the number of inverters of the signal generating circuit 100.The signal generating circuit 100 may comprise other circuits.

FIG. 7 is a circuit diagram of a booster power generating circuitaccording to a third embodiment of the invention. The arrangement of thebooster power generating circuit of the third embodiment will bedescribed with reference to FIG. 7.

The booster power generating circuit comprises a signal generatingcircuit 1A composed of a gate circuit, etc. and a charge pump circuit10A. The signal generating circuit 1A generates first and second pulsesignals S1 and S2 which complement each other, third and fourth pulsesignals S3 and S4 which complement each other, and fifth and sixth pulsesignals S5 and S6 which complement each other wherein the charge pumpcircuit 10A can output a given booster potential in response to thefirst and second pulse signals S1 and S2.

There are provided in the charge pump circuit 10A a first capacitor 11of a first booster circuit for boosting the potential of the first nodeN1 in response to the first pulse signal S1, a second capacitor 12 of asecond booster circuit for boosting the potential of the second node N2in response to the second pulse signal S2, a third capacitor 13 of athird booster circuit for boosting the potential of the third node N3 inresponse to the third pulse signal S3, a fourth capacitor 14 of a fourthbooster circuit for boosting the potential of the fourth node N4 inresponse to the fourth pulse signal S4, a fifth capacitor 15 of a fifthbooster circuit for boosting the potential of the fifth node N5 inresponse to the fifth pulse signal S5, and a sixth capacitor 16 of asixth booster circuit for boosting the potential of the sixth node N6 inresponse to the sixth pulse signal S6.

In the charge pump circuit 10A, there are provided an NMOS 22 as a firstprecharge circuit for precharging the second node N2 when controlled bythe third node N3, an NMOS 21 as a second precharge circuit forprecharging the first node N1 when controlled by the fourth node N4,NMOSs 24 and 28 as a third precharge circuit for precharging the fourthnode N4 when controlled by the third node N3, NMOSs 23 and 27 as afourth precharge circuit for precharging the third node N3 whencontrolled by the fourth node N4, an NMOS 29 as a fifth prechargecircuit for precharging fifth node N5 when controlled by the third nodeN3 and an NMOS 30 as a sixth precharge circuit for precharging the sixthnode N6 when controlled by the fourth node N4. There are additionallyprovided PMOSs 25 and 26 as first and second output circuits forrespectively outputting the boosted potential of each of the first andsecond nodes N1 and N2 to the output node NO.

The elements of the charge pump circuit 10A are connected with oneanother in the following manner. That is, the capacitor 11 receives atits one electrode the first pulse signal S1 from the pulse signalgenerating circuit 1A and it is connected to the first node N1 at itsother electrode. The capacitor 12 receives at its one electrode thesecond pulse signal S2 from the pulse signal generating circuit 1A andit is connected to the second node N2 at its other electrode. Thecapacitor 13 receives at its one electrode the third pulse signal S3from the pulse signal generating circuit 1A and it is connected to thethird node N3 at its other electrode. The capacitor 14 receives at itsone electrode the fourth pulse signal S4 from the pulse signalgenerating circuit 1A and it is connected to the fourth node N4 at itsother electrode. The capacitor 15 receives at its one electrode thefifth pulse signal S5 from the pulse signal generating circuit 1A and itis connected to the fifth node N5 at its other electrode. The capacitor16 receives at its one electrode the sixth pulse signal S6 from thepulse signal generating circuit 1A and it is connected to the sixth nodeN6 at its other electrode.

The first node N1 is connected to the source of the NMOS 21 and thedrain of the PMOS 25 while the second node N2 is connected to the sourceof the NMOS 22 and the drain of the PMOS 26. The third node N3 isconnected to the source of the NMOS 23 and the source of the NMOS 27 andthe gate of the NMOS 29 while the fourth node N4 is connected to thesource of the NMOS 24, the source of the NMOS 28 and the gate of theNMOS 30. The fifth node N5 is connected to the source of the NMOS 29 andthe gate of the PMOS 25 while the sixth node N6 is connected to thesource of the NMOS 30 and the gate of the PMOS 26. Each of the drains ofthe NMOSs 21, 22, 23, 24, 27, 28, 29 and 30 is connected to the powerpotential Vcc in which the gates of the NMOSs 23 and 24 are respectivelyconnected to the power potential Vcc. The sources of the PMOSs 25 and 26are connected to the output node NO.

FIG. 8 is a timing chart explaining the operation of the booster powergenerating circuit according to the third embodiment of the inventionshown in FIG. 7.

Each potential level of the first to sixth pulse signals S1 to S6 areshown in FIG. 8. α in FIG. 8 represents the potential which depends onthe charge consumption of a load circuit, not shown.

Supposing that in the booster power generating circuit each thresholdpotential of the NMOSs 21, 22, 23, 24, 27, 28, 29 and 30 is vtn and eachthreshold potential of the PMOSs 25 and 26 is vtp.

At time t1, the first pulse signal S1 is in the ground potential Vss andthe second pulse signal S2 is in the power potential Vcc and the thirdpulse signal S3 is in the ground potential Vss while the fourth pulsesignal S4 is in the power potential Vcc and the fifth pulse signal S5 isin the power potential Vcc and the sixth pulse signal S6 is in theground potential Vss. The first node N1 is in the power potential Vccand the second and output nodes N2 and NO are respectively in thepotential represented as 2Vcc-α while the third node N3 is in thepotential of Vcc and the fourth and fifth nodes N4 and N5 arerespectively in the potential of 2Vcc and the sixth node N6 is in thepower potential Vcc.

At time t2, if the fourth pulse signal S4 is changed from the powerpotential Vcc to the ground potential Vss, the fourth capacitor 14permits the potential of the fourth node N4 to be in the power potentialVcc. At this time, if the potential of the fourth node N4 becomes lessthan the potential expressed by Vcc+vtn, the NMOSs 21 and 30 arerespectively turned off so that the first, third and sixth nodes N1, N3and N6 are separated respectively from the power potential Vcc.

At time t3, if the sixth pulse signal S6 is changed from the groundpotential Vss to the power potential Vcc, the sixth capacitor 16 permitsthe sixth node N6 to be in the potential of 2Vcc. At this time, if thepotential of the node N6 is changed to the potential expressed by2Vcc-α-vtp, the NMOS 26 is turned off whereby the second node N2 and theoutput node NO are separated from each other. If the potential of thefirst pulse signal S1 is changed from the ground potential Vss to thepower potential Vcc, the first capacitor 11 permits the first node N1 tobe in the potential of 2Vcc.

At time t4, if the fifth pulse signal S5 is changed from the groundpotential Vss to the power potential Vcc, the fifth capacitor 15 permitsthe fifth node N5 to be in the potential of 2Vcc. At this time, if thepotential of the node N5 becomes less than the potential expressed by2Vcc-α-vtp, the NMOS 25 is turned on to thereby charge the potential ofthe output node NO until the latter reaches the potential expressed by2Vcc-α using the charge accumulated in the node N1. At the same time,the potential of the first node N1 is changed to the potential expressedby 2Vcc-α while discharging the charge. If the potential of the thirdpulse signal S3 is changed from the ground potential Vss to the powerpotential Vcc, the third capacitor 13 permits the third node N3 to be inthe potential of 2Vcc. At this time, if the potential of the third nodeN3 exceeds the potential expressed by Vcc+vtn, the PMOS 22 is turned onso that the potential of the second node N2 is discharged until itreaches the power potential Vcc.

At time t5, if the second pulse signal S2 is changed from the powerpotential Vcc to the ground potential Vss, the potential of the secondnode N2 is kept charged in the power potential Vcc although the secondcapacitor 12 intends to discharge the potential of the second node N2 tobe in the power potential Vcc since the NMOS 22 is turned on.

After time t5, the charge pump circuit 10A repeats the operations whichare performed during times t1 to t5 in response to the first, third andfifth pulse signals S1, S3 and S5 and the second, fourth and sixth pulsesignals S2, S4 and S6 which complement first, third and fifth pulsesignals S1, S3 and S5 so that the booster potential expressed by 2Vcc-αis generated in the output node NO.

As mentioned above, according to the third embodiment of the invention,there is obtained a high output potential compared with the conventionalbooster power voltage since there is not generated loss in the outputpotential by the threshold potential of vtp of the PMOS 25 and the PMOS26. Furthermore, it is possible to supply more charge by the potentialexpressed by vtp (C11+C12) supposing that the capacitances of the firstand second capacitors 11 and 12 are respectively C11 and C12 when usingthe same output potential as that of the conventional booster powergenerating circuit.

The third embodiment is not limited to that as mentioned above but itcan be modified as follows.

Even if the PMOSs 25 and 26 serving as the output circuits may comprisetransfer gates, the transfer gates can perform the effect of the thirdembodiment. The first to sixth precharge circuits may comprise resistorshaving high resistance.

INDUSTRIAL UTILIZATION

According to the first aspect of the invention, there is obtained highpotential between the first and third precharge circuits since there isno voltage drop of the boosted potential of the second and fourth nodes,and the precharging speed of the first and third node is not slowed,thereby outputting a given booster potential.

According to the second aspect of the invention, the potentials of thefirst and third nodes are not output to the power supply side by way ofthe first and third precharge circuits since the potential change of thesecond and fourth nodes can be performed quickly, thereby outputting agiven booster potential.

According to the third aspect of the invention, it is possible to supplythe boosted potential of the first and second nodes to the third nodewithout generating loss of the potential by the threshold potential ofthe transistors constituting the output circuit.

According to the fourth aspect of the invention, it is possible toreduce the current consumption of the circuit since the boosterpotential is supplied from the second and fourth booster circuits havingsmall capacitance while stopping first and third booster circuits havinglarge capacitance in case of small current consumption of the load. Itis also possible to output a given booster potential even if the currentconsumption of the load is large.

We claim:
 1. A booster power generating circuit comprising:a firstbooster circuit for supplying a first booster potential to a first nodein response to a first pulse signal; a second booster circuit forsupplying a second booster potential to a second node in response to asecond pulse signal; a third booster circuit for supplying a thirdbooster potential to a third node in response to a third pulse signal; afourth booster circuit for supplying a fourth booster potential to afourth node in response to a fourth pulse signal; a first prechargecircuit for precharging said first node upon reception of said fourthbooster potential from said fourth node; a second precharge circuit forprecharging said third node upon reception of said second boosterpotential from said second node; a first output circuit for outputtingsaid second and fourth booster potentials of said second and fourthnodes; and a second output circuit for outputting said first and thirdbooster potentials of said first and third nodes.
 2. A booster powergenerating circuit according to claim 1, wherein said first boostercircuit includes a first driving circuit which is controlled by a firstcontrol pulse signal.
 3. A booster power generating circuit according toclaim 1, wherein said first output circuit is controlled by a firstcontrol pulse signal.
 4. A booster power generating circuit according toclaim 1, further comprising a third precharge circuit for prechargingsaid second node.
 5. A booster power generating circuit according toclaim 1, further comprising a third precharge circuit for prechargingsaid fourth node.